The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs. The intended use for this standard is IC timing and power. This standard may be applied to both unit logic cells supplied by the IC vendor and logical macros defined by the IC designer. Although this standard is written toward the integrated circuit supplier and EDA developer, its application applies equally well to representation of timing and power for designer-defined macros (or hierarchical design elements).
As feature sizes for chips shrink below 0.5 μ m, interconnect delay effects outweigh those of the logic cells. This means placement of cells and wire routing of the interconnects become as important a factor as the type of cell drivers and receivers on the interconnect. As a result, EDA logic design applications (such as synthesis) now need to interact closely with physical design applications (such as floorplanning and layout). Applications that before could consider only simple delay and power models now need to deal with complex delay and power equations. The designer now needs EDA applications that can be directed to specific timing constraints, and provide consistent and accurate characterization of a chip’s timing and power before it is manufactured. Plus, due to the complexities of the delay and power equations, the integrated circuit vendor needs to have control of application calculations and not be restricted by unique characteristics of the broad set of applications demanded by the customers (or designers).
New IEEE Standard – Superseded. Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.
As feature sizes for chips shrink below 0.5 μ m, interconnect delay effects outweigh those of the logic cells. This means placement of cells and wire routing of the interconnects become as important a factor as the type of cell drivers and receivers on the interconnect. As a result, EDA logic design applications (such as synthesis) now need to interact closely with physical design applications (such as floorplanning and layout). Applications that before could consider only simple delay and power models now need to deal with complex delay and power equations. The designer now needs EDA applications that can be directed to specific timing constraints, and provide consistent and accurate characterization of a chip’s timing and power before it is manufactured. Plus, due to the complexities of the delay and power equations, the integrated circuit vendor needs to have control of application calculations and not be restricted by unique characteristics of the broad set of applications demanded by the customers (or designers).
New IEEE Standard – Superseded. Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.
