Add mutual exclusion semantics to the shared variable feature in VHDL.
To address a language feature area that received a significant share of negative ballots and positive ballots with comments on the implementation during the successful VHDL 1076-1993 balloting. The working group was formed to attempt to reach consensus on a better implementation of the language feature.
Revision Standard – Superseded. VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language.
To address a language feature area that received a significant share of negative ballots and positive ballots with comments on the implementation during the successful VHDL 1076-1993 balloting. The working group was formed to attempt to reach consensus on a better implementation of the language feature.
Revision Standard – Superseded. VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language.
